Energy Efficient Acceleration Of Floating Point Applications Onto Cgra

In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications. Experimental results show that the proposed accelerator achieves a maximum of 4.61x speedup compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative of wide range of EEG signal processing applications with an area overhead of 1.9x. The proposed CGRA achieves a maximum of 6.5x energy efficiency compared to the CPU.