Accelerating the VVC Decoder for Vector Length Agnostic SIMD Architectures

The standardization of the next-generation video standard, the Versatile Video Coding (VVC), is nearing completion. At the same time, new architectures for Single Instruction Multiple Data (SIMD) extensions are entering the market. They implement a vector length agnostic approach, i.e. code can be vectorized independently of the target hardware vector size and is therefore portable across different platforms. We have taken the VVC decoder and explored the speedup potential of such architectures by implementing the three most time-consuming kernels with ARM's Scalable Vector Extensions (SVE). Results show that we are able to speed up individual kernels by up to a factor of 3x, while the overall decoding speed increases by 18% to 29% on average, depending on the quantization parameter. Not all kernels benefit from increasing vector lengths, however, and we observe a diminishing return on investment for vector sizes larger than 512 bit.